The present invention relates to a data input buffer used in a semiconductor memory device and particularly to a data input buffer which is not affected by the variation of the power source voltage.
In the semiconductor memory device, each pin is equipped with data input buffers which convert the TTL level signal inputted from the outside into a C-MOS level signal usable in the inside of the semiconductor memory device.
In order to satisfactorily buffer address signals and various control signals which are applied from the outside of semiconductor memory chip, the stability of data input buffer operation is required.
In the general data input buffer, an input trip level is set to determine a predetermined logic state from the TTL level signal which enters from the outside. The trip level is determined according to the size of C-MOS transistor which constitutes a buffer. However, variation of power source voltage lowers the reliability of buffer by making the input trip level unstable.
Referring to FIG. 1A the conventional data input buffer circuit is shown, the conventional data input buffer is connected to power source voltage terminal V.sub.cc through P-MOS transistor 1 which is controlled by a buffer enable signal EN. The input voltage V.sub.in, which is applied by a TTL level outside signal, is connected in common to P-MOS transistor 2, N-MOS transistor 4 and gate 5. The potential of sensing node 3 which connects the drain of said P-MOS transistor 2 and the drain of said N-MOS transistor 4 attains to output voltage V.sub.out, a final output of data input buffer, through inverter 6 and the output voltage V.sub.out is supplied to the inside chip.
FIG. 1B shows the voltage variation (10 V) of the source terminal 10 of P-MOS transistor 2 according to the variation of the power source voltage V.sub.cc FIG. 1C shows an input trip margin (or the amount of voltage which varied between source and drain) of P-MOS transistor 2 according to the variation of the power source voltage in the circuit of the FIG. 1A, when the level of the input voltage V.sub.in is inputted is lower than 0.8 V, the P-MOS transistor 2 turns on and a level of output voltage V.sub.out attains to a low state. When the circuit operates, the voltage V10 of the source terminal 10 of the P-MOS transistor 2 is in V.sub.cc -.alpha. condition (.alpha. is a voltage drop by P-MOS transistor) because the buffer enable signal EN is in a low state. When the P-MOS transistor 2 turns on and an electric current flows, the voltage V10 drops. However, the voltage V10 rises from the initial value V.sub.cc -.alpha. when power source voltage V.sub.cc rises, as illustrated in FIG. 1A. Due to a rise voltage V10 of the source terminal 10, a difference of gate-to-source voltage .vertline.V.sub.in -V10.vertline. of P-MOS transistor 2 increases. Therefore, voltage appearing in the sensing node 3 (or input trip margin ITMG) rises according to a rise in power source voltage V.sub.cc, as illustrated in the graph of FIG. 1C. In other words, input level trip margin expands because the difference of gate-to source voltage V.sub.GS =.vertline.V.sub.in -V10.vertline. of P-MOS transistor 2 increases due to a rise in V10 consequent on a rise in power source voltage V.sub.cc.
Consequently, in such a conventional circuit as stated above, output voltage shows a high state even when input level is higher than 0.8 V, not to speak of when the input level is lower than 0.8 V. Even in the case where power source voltage drops abnormally, an input trip margin ITMG of the P-MOS transistor 2 also increases as in the case where the power source voltage rises. In this case, a low state can be outputted if input level is lower than 2.4 V.